Tunable Steep Slope MoS2 Transistor

Dr. Navakanta Bhat

The CMOS scaling is now facing serious fundamental and technological challenges resulting in diminishing performance and economic returns. The concurrent reduction in power consumption, an important aspect of scaling, has become difficult, because of the inability to reduce supply voltage below 1 V. This is primarily because the fundamental nature of charge transport governed by Boltzmann’s statistics restricts the Sub-threshold Swing (SS, abruptness between OFF to ON transitions) of FETs to the thermionic limit of 60 mV/dec at room temperature. Hence, as we cram in more transistors into the same footprint, energy dissipation and heat management become fundamental bottlenecks. Clearly, the road ahead needs breakthroughs in new materials and device design.
In this talk, a new device architecture will be presented, to beat the Boltzmann limit. For the first time, sub-thermionic transport through tunable Schottky contacts in dual gated MoS2 FETs will be demonstrated. Two device configurations the gate tunable thermionic tunnel transistor (GT3) and dynamic Vt and adaptable transport transistor (DVAT) are expounded. The GT3 transistor has the flexibility to operate either in the sub-thermionic tunnel regime, yielding steep SS<60 mV/dec OR thermionic high mobility regime. Combining the best of both tunneling and thermionic regimes in the same operation cycle, the DVAT transistor, the closest to an ‘ideal transistor’, registers SS~29 mV/dec (3 dec) AND high mobility (100 cm2V-1s-1). This work is envisioned to pave a new path in the development of sub-thermionic, high performance FETs operating in the sub-0.5 V ‘green computing’ regime.

Dr. Navakanta Bhat

Navakanta Bhat received his B.E. in Electronics and Communication from SJCE, University of Mysore in 1989, M.Tech. in Microelectronics from I.I.T. Bombay in 1992 and Ph.D. in Electrical Engineering from Stanford University, Stanford, CA in 1996. Then he worked at Motorola’s Networking and Computing Systems Group under Advanced Products R&D Lab (APRDL)  in Austin, TX until 1999. At Motorola he worked on logic technology development and he was responsible for developing high performance transistor design and dual gate oxide technology. He joined the Indian Institute of Science, Bangalore in 1999 where he is currently a Professor and Chair, Centre for Nano Science and Engineering. His current research is focused on Nanoelectronics device technology, Biosensors for point of care diagnostics and Gas sensors for pollution monitoring. He has 240 research publications in international journals and conferences and 10 granted US patents and 14 pending patents to his credit. He was instrumental in creating the National Nanofabrication Centre (NNfC) at IISc, Bangalore, benchmarked against the best university facilities in the world. He served as the chairman of NNfC administration committee from 2010 to 2015.

He is a Fellow of the Indian National Academy of Engineering. He has received the Young Engineer Award (2003) from the Indian National Academy of Engineering, Swarnajayanti fellowship (2005) from the Department of Science and Technology, Govt. of India and Prof. Satish Dhavan award (2005) from the Govt. of Karnataka. He is also the recipient of IBM Faculty award 2007 and Outstanding Research Investigator award (2010) from DAE. For his translational research work, he has received the prestigious Dr. Abdul Kalam Technology Innovation National Fellowship (2018) and Prof. Rustum Choksi award for Excellence in Engineering Research (2017).

He is a senior member of IEEE, and is currently (2016-2019) a member of the Board of Governors of the IEEE Electron Devices Society and also the Chair of Nanotechnology technical committee. He was the Editor of IEEE Transactions on Electron Devices, (2013-2015),  and currently the chief-editor of the IEEE TED special issue on “2D Materials for Electronic, Optoelectronic and Sensors”. He was the founding chair of the IEEE Electron Devices and Solid-State Circuits society, Bangalore chapter which was recognized as the Outstanding Chapter of the Year by the IEEE SSC society (2003) and IEEE EDS society (2005). He was the technical program chair for the International Conference on VLSI design and Embedded Systems (2007) and co-General chair of the International conference on Emerging Electronics (2012). He is a Distinguished Lecturer of the IEEE Electron Devices Society.

He was the Chairman of the Human Resource Development and Infrastructure committee of the National Program on Micro and Smart Systems. He was the member of the committee set up by the Principal Scientific Advisor to Govt. of India to recommend strategies to develop semiconductor manufacturing ecosystem in India.

He is the founder and promoter of a startup company, PathShodh Healthcare Pvt Ltd (www.pathshodh.com).   Based on his group’s research in biosensors, PathShodh has developed the first of its kind multi-analyte point-of-care diagnostic device for 5 blood tests and 3 urine tests, related to multiple chronic diseases including diabetes and its complications, anemia and malnutrition, kidney and liver diseases. For this technology, PathShodh has received multiple recognitions : Confederation of Indian Industry (CII) Industrial Innovation Award 2017, for the most promising start-up and CII Grand Jury Award for Innovation, 2017; Federation of Indian Chambers of Commerce and Industry (FICCI) Healthcare Excellence award, 2017 for the best start-up of the year. PathShodh’s product has  already been used for rural health screening. Notable among them is the partnership with Tata Trust in deploying PathShodh technology for rural Telemedicine project serving several villages in Andhra Pradesh and Uttar Pradesh.